1. Field
This invention relates to electronic circuit wiring nets, and more specifically to noise analysis for electronic circuit wiring nets.
2. Background
Moment-matching techniques like Asymptotic Waveform Evaluation (AWE) are very popular throughout the industry for calculating delay and noise for the interconnects between gates which dominate our current designs. NoisePad, Cross-Cap, iBEST, TANGO and Primetime, EinsTimer, Global Harmony, and Clarinet are examples of tools that use these current techniques. A common problem in all noise tools (and timing tools that deal with noise push out) is the calculation of the effect of noise at the receiver end of an interconnect (i.e., signal net), especially when there are hundreds of adjacent nets represented as capacitors (also known as attackers) with signals coupling to the interconnect under analysis. Each of these coupling capacitors usually requires a separate analysis of the interconnect to calculate the noise at the receiver. The tools described above use the efficiency of rapid interconnect circuit evaluator (RICE), which is a fast frequency domain circuit analyzer based on the AWE theory, to solve the resulting run time problem. Despite the efficiency of RICE, a problem still exists when the number of attacker is large. As a result, tools resort to a set of pruning techniques to reduce the number of attackers.
FIG. 1 shows a diagram of a typical on-chip net with several neighboring nets that couple to it. Driver 10 sends signals on net 14 to receiver 12. Neighboring nets, e.g., 16-19 (shown as rectangles) may be close to net 14 with their own set of signals. The several attacker nets 16-19 can couple with net 14 under consideration. The exact transition times of the attacker signals cannot be accurately determined because of the effect of coupling on the signal wave shape. Further, the timing windows in which each attacker signal effects the net under consideration cannot be accurately determined because of the uncertainty associated with the delays through the circuitry of the attacker signals.
FIG. 2 shows a schematic diagram of an equivalent circuit for noise modeling. Driver 10 drives signals through net 14 to receiver 12 represented by receiver capacitance 18. Each attacker net is represented by a voltage source 20 and a capacitor 22. The circuit model in FIG. 2 may be used where the transition times of the attacker signals VSi are set to a conservatively low value. The lower the value of the transition time, the higher the noise at the receiver. If the driver of the victim net under consideration is modeled as a grounded resister then the entire equivalent circuit can be treated as an n-port linear system, where ports refer to the nodes and the circuit where the excitation sources, i.e., voltage sources, are attached. Since the timing windows of attacker signals cannot be accurately determined, the worst case noise signal may be assumed where the attacker signals align such that the peaks of the noise signals due to each attacker coincide. This is known as the peak alignment and represents the maximum amplitude signal at the receiver.
Currently, the following procedure is used to determine the worst case noise: (1) for each attacker capacitor, a voltage source is attached with a ramp time equal to the estimated transition time for the attacker; all other attacker capacitors are grounded; and the resulting circuit is analyzed to determine the noise signal at the receiver; (2) the noise signals for each attacker are aligned so that the peaks of the noise signals coincide; and (3) the resulting individual noise signals are added to determine the worst case composite noise signal. However, analyzing the resulting circuit to determine the noise signal at the receiver involves analyzing the entire circuit (with a single excitation though) and is very time consuming.